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NCP1581 High Frequency Synchronous Step Down PWM Controller for Tracking Applications
The NCP1581 controller IC is designed to provide a simple synchronous buck regulator for on-board DC to DC applications in a 14-pin SOIC. The NCP1581 is designed specifically for tracking applications by providing the track input. The NCP1581 operates at a fixed internal 400 kHz switching frequency allowing the use of small external components. The device features a programmable soft start set by an external capacitor, under-voltage lockout and output under-voltage detection that latches off the device when an output short is detected.
Features http://onsemi.com MARKING DIAGRAM
NCP1581G AWLYWW 1
14 1 A WL Y WW G
SOIC-14 D SUFFIX CASE 751A = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * * * *
Power up Sequencing / Tracking Enable Input Internal 400 kHz Oscillator Programmable Soft-Start Fixed Frequency Voltage Mode Voltage Mode Adaptive Deadtime This is a Pb-Free Device Tracking Applications Game Consoles Computing Peripheral Voltage Regulators Graphics Cards General DC to DC Converters
PIN CONNECTIONS
FB VP NC VCC NC LDRV GND (Top View) 1 NC SS COMP NC VC HDRV PGND
Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
NCP1581
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2010
January, 2010 - Rev. 0
1
Publication Order Number: NCP1581/D
Block Diagram
Circuit Description:
VCC POR VP/EN 0.65V FAULT Delay
VC
V CC UVLO HDRV
GND
V BIAS POR Q 64uA Max 2V SS POR R Q 0.4V S POR CT Reset Dom R Oscillator PWM S
2V
2 2 uA
NCP1581
Figure 2. Simplified Block Diagram
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POR Error Amp Error Comparator FAULT
2
SS
VCC 2V
VP/EN
Delay
LDRV
FB
25k
COMP
25k
PGND
NCP1581
Table 1. PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 Name FB VP/EN NC VCC NC LDRV GND PGND HDRV Description Inverting input to the error amplifier. This pin is connected to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Dual function pin. Non inverting input to the error amplifier. Enable input. No Connect This pin provides power for the internal blocks of the IC as well as powers the low side driver. A minimum of 0.1 mF, high frequency capacitor must be connected from this pin to power ground. No Connect Output driver for low side MOSFET. IC ground for internal control circuitry. Power Ground. This pin serves as a separate ground for the MOSFET drivers and should be connected to the system's power ground plane. Output driver for high side MOSFET. The negative voltage at this pin may cause instability for the gate drive circuit. To prevent this, a low forward voltage drop diode (e.g. BAT54 or 1N4148) is required between this pin and Power Ground. This pin powers the high side driver. No Connect Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. Soft start. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to ground to set the start up time of the output voltage. No Connect
10 11 12 13 14
VC NC COMP SS NC
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating Main Supply Voltage Input Main Supply Voltage Input 200 ns wide spikes, 400 kHz Symbol VCC VCC_SPK VC VC_SPK VP/EN VFB Rating Thermal Resistance, Junction-to-Ambient (Note 2) Storage Temperature Range Junction Operating Temperature ESD Withstand Voltage (Note 3) Human Body Model Machine Model Moisture Sensitivity Level Symbol Rthja Tstg TJ VESD 2.0 200 MSL JEDEC Level 1 @ 260C kV V min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 max 20 22 20 22 10 or VCC (Note 1) 10 or VCC (Note 1) Value 90 -65 to 150 0 to 150 Unit V V V V V V Unit K/W C C
Supply Voltage for the High side driver Supply Voltage for the High side driver 200 ns wide spikes, 400 kHz VP/EN pin Voltage FB pin Voltage
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: All voltages are referenced to GND pin unless otherwise stated. 1. Maximum = 10 V or VCC, whichever is lower. 2. JEDEC High-K model 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 Machine Model (MM) 200 V per JEDEC standard: JESD22-A115
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NCP1581
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol VCC VC TJ Definition Supply Voltage Supply Voltage Junction Temperature Min 7 Converter Voltage + 5 V, (Note 4) 0 Max 20 20 125 Units V V C
NOTE: All voltages are referenced to GND pin. 4. Depend on high side MOSFET VGS
Table 4. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0C < TJ < 125C
Parameter SUPPLY CURRENT VCC Supply Current (Static) VCC Supply Current (Dynamic) VC Supply Current (Static) VC Supply Current (Dynamic) UNDER VOLTAGE LOCKOUT VCC-Start-Threshold VCC-Stop-Threshold VCC-Hysteresis Enable-Start-Threshold Enable-Stop-Threshold Enable-Hysteresis FB UVLO OSCILLATOR Frequency Ramp Amplitude Min Duty Cycle Max Duty Cycle ERROR AMPLIFIER FB Input Bias Current FB Input Bias current VP/EN Input Bias Current Transconductance Input Offset Voltage VP/EN Common Mode Range IFB1 IFB2 IVP/EN gm VOS VCOMN IOTA (SINK) IOTA (SOURCE) VP/EN = 0.8 V, VCOMP = 2.0 V (Note 5) VSS = 3 V VSS = 0 V VSS = 3 V 440 -6 0.6 0 -0.1 64 -0.1 -0.5 1300 +6 1.5 -0.5 mA mA mA mmho mV V fSW VRAMP DMIN DMAX (Note 5) VFB =1V, VP/EN = 0.8 V fSW = 400 kHz, VFB = 0.6 V, VP/EN = 0.8 V 83 85 370 400 1.25 0 95 430 kHz V % % VCC UVLO (R) VCC UVLO (F) VCC (Hyst) VP/EN UVLO (R) VP/EN UVLO (F) VP/EN (Hyst) VFB UVLO Supply voltage Rising Supply voltage Falling Supply ramping up and down Supply voltage Rising Supply voltage Falling Supply ramping up and down FB ramping down 0.3 6.3 6.0 0.2 0.6 0.56 6.6 6.3 0.3 0.65 0.6 40 0.4 0.5 7.0 6.6 0.4 0.7 0.66 V V V V V mV V ICC(Static) ICC(Dynamic) IC(Static) IC(Dynamic) VP/EN = 0 V, No Switching fSW = 400 kHz, CL = 1.5 nF VP/EN = 0 V, No Switching fSW = 400 kHz, CL = 1.5 nF 1.5 10 0.05 9 3 15 0.1 15 mA mA mA mA Symbol Test Condition Min Typ Max Units
ERROR AMPLIFIER DESIGN SPECIFICATIONS OTA output current OTA output current VFB = 1.2 V, VP/EN = 1.0 V, VCOMP = 2.0 V, (Note 5) VFB = 0.8 V, VP/EN = 1.0 V, VCOMP = 2.0 V, (Note 5) 100 100 mA mA
5. Guaranteed by Design but not tested in production.
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NCP1581
Table 5. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0C < TJ < 125C
Parameter SOFT START Soft Start Current Soft Start Turn On OUTPUT DRIVERS LO Drive Rise Time HI Drive Rise Time LO Drive Fall Time HI Drive Fall Time Dead Band Time Adaptive DBT Level tr(Lo) tr(Hi) tf(Lo) tf(Hi) tDEAD VADT tr(Hi) 9V High Side Driver (HDRV) 2V tr(Lo) 9V Low Side Driver (LDRV) 2V tf(Hi) CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) (See Figure 3) 35 20 30 20 30 45 2.0 50 60 50 60 90 ns ns ns ns ns V ISS SS (on) VSS = 0 V 12 1.8 22 2 32 2.2 mA V Symbol Test Condition Min Typ Max Units
tDEAD
tDEAD
tf(Lo)
Figure 3. Definition of Rise/Fall Time and Deadband Time
TYPICAL CHARACTERISTICS
7.00 6.90 6.80 6.70 VCC (V) 6.60 6.50 6.40 6.30 6.20 6.10 6.00 Falling Rising
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 4. VCC UVLO http://onsemi.com
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NCP1581
TYPICAL CHARACTERISTICS
0.70 0.68 0.66 VP/EN (V) 0.64 0.62 0.60 0.58 0.56 0 20 40 60 80 100 120 Falling Rising VFB (V) 0.50 0.48 0.46 0.44 0.42 0.40 0.38 0.36 0.34 0.32 0.30
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. VP/EN UVLO
95 93 91 DMAX (%) 89 87 85 83 81 0 20 40 60 80 100 120 fSW (kHz) 440 430 420 410 400 390 380 370 360 0 20
Figure 6. FB UVLO
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. Maximum Duty Cycle
1300 1200 1100 1000 gm (mmho) t (ns) 900 800 700 600 500 400 0 20 40 60 80 100 120 90 80 70
Figure 8. Switching Frequency
Low to High 60 50 40 30 High to Low
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. Error Amplifier Transconductance
Figure 10. Deadtime
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NCP1581
Detailed Description
Introduction
The NCP1581 is voltage mode PWM synchronous controller designated to drive two external N-channel MOSFETs. Switching frequency is fixed at 400 kHz. Output voltage is determined by feedback resistor divider and external reference voltage. Reference voltage input can be used to enabling and disabling operation and for tracking function.
Under-Voltage Lockout
The value of the output capacitor should be calculated using the following equation:
C OUT w DI L 8 @ f SW @ (DV OUT * DI L @ ESR)
(eq. 3)
The undervoltage lockout circuit ensures that the IC does not start and work until VCC and VP/EN are over set thresholds. If these conditions are not fulfilled output drivers are in the off state.
Disable Function
For a higher switching frequency, it is suitable to use a multilayer ceramic capacitor (MLCC) with very low ESR. The advantages are small size, low output voltage ripple and fast transient response. The disadvantage of the MLCC type is the requirement to use a Type III compensation network.
Input Capacitor Selection
The output voltage can be disabled by pulling the VP/EN pin below 0.6 V. At this time are output drivers in the off state.
Output Voltage
The input capacitor is used to supply current pulses while the high side MOSFET is on. When the MOSFET is off, the input capacitor is being charged. The value of this capacitor can be selected with the Equation (4):
I OUT @ C IN w
VOUT VIN
@ 1*
VOUT VIN (eq. 4)
f SW @ DV IN
Output voltage can be set by an external resistor divider and external reference voltage at VP/EN pin according to Equation (1):
V OUT + V P
EN @
1 ) R1 R2
(eq. 1)
where DVIN is the input voltage ripple and the recommended value is about 2-5% of VIN. The input capacitor must be able to handle the input ripple current. Its value should be calculated using Equation (5):
V OUT @ 1 * I RMS + I OUT @ Power MOSFET Selection V IN VOUT V IN
(eq. 5)
where VP/EN is the external reference voltage at VP/EN pin that is connected to noninverting input of error amplifier. R1 and R2 resistors create voltage divider from output to FB pin that is connected to inverting input of error amplifier. Absolute values of resistors R1 and R2 depend on the compensation network type. See discussion of compensation description for details.
Inductor Selection
The inductor selection is based on the output power, frequency, input and output voltages, and efficiency requirements. High inductor values cause low current ripple, slower transient response, higher efficiency and increased size. Inductor design can be reduced to desired maximum current ripple in the inductor. It is good to have current ripple (DILmax) between 20% and 50% of the output current. For a buck converter, the inductor should be chosen according to Equation (2).
L+ V OUT f SW @ DI Lmax 1* V OUT V INmax
(eq. 2)
The NCP1581 uses two N-channel MOSFETs. They can be primarily selected according to RDS(ON), maximum drain to source voltage, and gate charge. RDS(ON) impacts conductive losses and gate charge impacts switching losses. The low side MOSFET is selected primarily for conduction losses, and the high side MOSFET is selected to reduce switching losses especially when the output voltage is less than 30% of the input voltage. The drain to source breakdown voltage must be higher than the maximum input voltage. Conductive power losses can be calculated using the following Equations (6) and (7):
P COND-HIGHFET + I OUT 2 @ R DS(ON) @ P COND-LOWFET + I OUT 2 @ R DS(ON) @ 1 * V OUT (eq. 6) V IN
(eq. 7)
V OUT V IN
Output Capacitor Selection
The output voltage ripple and transient requirements determine the output capacitor type and value. The important parameter for the selection of the output capacitor is equivalent serial resistance (ESR). If the capacitor has low ESR, it often has sufficient capacity for filtering as well as an adequate RMS current rating.
Switching losses are dependent on the drain to source voltage at turn-off state, output current, and switch-on and switch-off times, as is shown by Equation (8).
P SW + V DS(OFF) 2 @ (t ON ) t OFF) @ f SW @ I OUT
(eq. 8)
tON and tOFF times are dependent on the transistor gate charge.
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NCP1581
The MOSFET output capacitance loss is caused by the charging and discharging during the switching process and can be computed using Equation (9).
P COSS + C OSS @ V IN 2 @ f SW 2
(eq. 9)
that of the body diode, and reverse recovery time (trr) should be lower then that of the body diode. The Schottky diode's capacitance loss can be calculated as shown in Equation (11).
P C(schottky) + Adaptive Deadtime C schottky @ V IN 2 @ f SW 2
(eq. 11)
where COSS = CDS + CGS. Some power dissipation is caused by the reverse recovery charge in the low side MOSFET body diode, which conducts at dead time. This charge is needed to close the diode. The current from the input power supply flows through the high side MOSFET to the low side MOSFET body diode. This power dissipation can be calculated using the following Equation (10):
P QRR + Q RR @ V IN @ f SW
(eq. 10)
QRR is the diode recovery charge as given in the manufacturer's datasheet. For some types of MOSFETs, this dissipation may be dominant at high input voltages. It is necessary to take care when selecting a MOSFET. An external Schottky diode across the low side MOSFET can be used to eliminate the reverse recovery charge power loss. The Schottky diode's forward voltage should be lower than
The NCP1581 includes voltage mode adaptive dead time feature. This block waits for full turn off of the one of MOSFETs before the second one can be turned on. Detection is based on driver voltage, when this voltage drops below VADT second driver can be turned on. There is fixed time tDEAD between turn off detection and internal logical turn on signal that increase safety. There can't be used additional gate resistors due to voltage base detection, because these resistors would create voltage divider with driver's pull down transistor and correct turn off detection is impossible. Gate resistors may be used only if MOSFETs turn off time is at all operation conditions shorter than tDEAD. MOSFETs' timing diagram can be seen at Figure 11.
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NCP1581
tDEAD tDEAD
High Side Logic Signal
Low Side Logic Signal
HDRV VADT
LDRV VADT
t d (on ) R DSmax High Side MOSFET R DS R DS (ON )min tr
tf
t d (off ) tr tf
R DSmax Low Side MOSFET R DS R DS (ON )min t d (on ) t d (off)
Figure 11. MOSFETs Timing Diagram Soft Start
The soft start time is set by a capacitor connected between the SS pin and ground. This function is used for controlling the output voltage slope and limiting start-up currents. The start-up sequence initiates when the Power On Ready (POR) internal signal rises to logic level high. That means the supply voltage and VP/EN voltage are over the set thresholds. The soft start capacitor is charged by a 22 mA current source. If POR is low, the SS pin is internally pulled to GND, which
means that the NCP1581 is in a shutdown state. The SS pin voltage (0 V to 2 V) controls the internal current source (64 mA to 0 mA) with a negative linear characteristic. This current source injects current into the resistor (25 kW) connected between the FB pin and the negative input of the error amplifier and into the external feedback resistor network. Voltage drop on these resistors is over 1.6 V, which is enough to force the error amplifier into a negative saturation state and to block switching.
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NCP1581
When the soft start pin reaches around 1.2 V (exact value depends on feedback and compensation network and on the soft start capacitor; a larger soft start capacitor and a lower compensation capacity decrease this level), the IC starts switching. The impact of the controlled current source decreases and the output voltage starts to rise. When the soft start capacitor voltage reaches 2 V, the output voltage is at nominal value. The soft start time must be at least 10 times longer than the time needed to charge the compensation network from the output of the error amplifier. If the soft start time is not long enough, the soft start sequence would be faster than the charging compensation network and the IC would start without slowly increasing the output voltage. The soft start capacitance can be calculated using Equation 12:
C SS + 22 @ 10 -6 @ T SS
(eq. 12)
VCC = VC
VIN
VP_EN
POR
3V VSS 0V VOUT 1V 2V
Internal IFB
64 mA
Vneg_error_amp
>1.6 V
VP/EN VP/EN
VFB 0V
Figure 12. Start-up Sequence Start to Pre-biased Output
The NCP1581 is able to start up into a pre-biased output capacitor. The low side MOSFET does not turn on before the output voltage is at set value. During this time, the energy is
not discharged by the low side MOSFET (current flows through low side MOSFET body diode) until the soft start sequence ends.
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NCP1581
Vout
VSS 1V
3V 2V
VLDRV
VHDRV
Figure 13. Start-up to Pre-biased Output Short Circuit Protection
The output of convertor with NCP1581 is protected against short circuit conditions. This protection is sensing output voltage through feedback divider on FB pin. On this
VCC or VP/EN
pin is comparator that compares FB voltage to 0.4 V. If FB voltage is below 0.4 V then IC goes to latch state and switch output drivers to off state. Latch state can be released by decrease VCC or VP/EN voltage below threshold.
Threshold
Vout
Output shorted
VSS
VLDRV
VHDRV
Figure 14. Short Circuit Protection (Start Up, Short, Latch, Latch Release and New Start-up)
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NCP1581
Compensation Circuit
The NCP1581 is a voltage mode buck converter with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows:
f PO + 1 2 @ p @ L @ C OUT
(eq. 13)
One zero of this LC filter is given by the output capacitance and output capacitor ESR. Its value can be calculated using the following equation:
f Z0 + 1 2 @ p @ C OUT @ ESR
(eq. 14)
The next parameter that must be chosen is the zero crossover frequency f0. It can be chosen to be 1/10-1/5 of the switching frequency. These three parameters show the necessary type of compensation that can be selected from Table 6.
Table 6. COMPENSATION TYPES
Zero Crossover Frequency Condition fP0 < fZ0< f0 < fSW/2 fP0 < f0< fZ0 < fSW/2 fP0 < f0 < fSW/2 < fZ0 Compensation Type Type II (PI) Type III (PID) Method I Type III (PID) Method II Typical Output Capacitor Type Electrolytic, Tantalum Tantalum, Ceramic Ceramic
Compensation Type II (PI)
Compensation Type III (PID)
This compensation is suitable for low-cost electrolytic capacitors. The zero created by the capacitor's ESR is a few kHz, and the zero crossover frequency is chosen to be 1/10 of the switching frequency. Components of the PI compensation (Figure 15) network can be specified by the following equations:
VOUT
Tantalum and ceramic capacitors have lower ESR than electrolytic capacitors, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This situation needs to be compensated by the PID compensation network that is shown in Figure 16.
VOUT CC2 RFB1
R1 - + R2 VP/EN *Optional OTA RC1 CC1 CC2*
R1 CFB1 RC1 - OTA + CC1
R2
VP/EN
Figure 15. PI compensation (Type II) 2 @ p @ f 0 @ L @ V RAMP @ V OUT R C1 + ESR @ V IN @ V P EN @ gm C C1 + C C2 + R1 + 1 0.75 @ 2 @ p @ f P0 @ R C1 1 p @ R C1 @ f SW
EN
Figure 16. PID Compensation (Type III)
(eq. 15)
There are two methods to select the zeros and poles of the compensation network. The first one (method I) is usable for tantalum output capacitors, which have a higher ESR than ceramics, and its zeros and poles can be calculated as shown below:
f Z1 + 0.75 @ f P0 f Z2 + f P0 f P2 + f Z0 f P3 + f SW 2
(eq. 16)
V OUT * V P VP
EN
@ R2
VRAMP is the peak-to-peak voltage of the oscillator ramp, and gm is the transconductance error amplifier gain. Capacitor CC2 is optional.
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NCP1581
The second one (method II) is for ceramic capacitors:
f Z2 + f 0 @ f P2 + f 0 @ 1 * sin q max 1 ) sin q max 1 ) sin q max 1 * sin q max
The remaining calculations are the same for both methods.
2 R C1 uu gm C C1 + 1 2 @ p @ f Z1 @ R C1 1 2 @ p @ f P3 @ R C1 2 @ p @ f 0 @ L @ V RAMP @ C OUT V IN @ R C1 1 2 @ p @ C FB1 @ f P2
(eq. 18)
(eq. 17)
f Z1 + 0.5 @ f Z2 f P3 + 0.5 @ f SW
C C2 +
C FB1 + R FB1 + R1 +
1 * R FB1 2 @ p @ C FB1 @ f Z2 V P EN R2 + @ R1 V OUT * V P EN
To check the design of this compensation network, the following equation must be true:
R1 @ R2 @ R FB1 1 u gm (eq. 19) R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2
If it is not true, then a higher value of RC1 must be selected.
ORDERING INFORMATION
Device NCP1581DR2G Package SOIC-14 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP1581
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE J
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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